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Without a separate interrupt stack each task stack would have to allocated enough space to hold an entire potentially nested interrupt stack frame.
Supports interrupt stack overflow detection in addition to the standard task stack overflow detection. Provides a full interrupt nesting model that does not, itself, ever completely disable interrupts. Although the MIPS hardware disables interrupts on entry to an interrupt service routine the RTOS code quickly re-enables them before any application handler code is executed.
Listing 1: Assembly code wrapper for handling an interrupt that can cause a context switch. All rights reserved. Click here to view a static menu.
The demo project can be configuration to build either a simple blinky demo or a comprehensive test and demo application. The comprehensive application demonstrates and tests the interrupt nesting behaviour. Build instructions are provided on this page. See the Source Code Organization section for a description of the downloaded files, and information on creating a new project. The Blinky Software Timer: This demonstrates an auto-reload software timer. The timer callback function does nothing but toggle an LED.
The task sits in a loop that sends the value to the queue every milliseconds. The task sits in a loop blocking on attempts to read from the queue no CPU cycles are consumed while it is blocked , toggling an LED each time a value is received. As the queue send task writes to the queue very milliseconds the queue receive task unblocks and toggles the LED every milliseconds. The second LED is under the control of a task that is triggered by an interrupt.
It is provided as an example of how to write a FreeRTOS compatible interrupt service routine RTOS compatible interrupt service routines are also described on this page. The software timer is used to monitor all the other tasks, and to toggle an LED. If all the other tasks are executing as expected the LED will toggle every 3 seconds. If a suspected error has been found in any of the other tasks the toggle rate will increase to ms. Interrupt nesting is exercised using one task and two interrupts — all of which access the same two queues.
The two interrupts run at different priorities, and both run above the RTOS kernel interrupt priority, meaning a maximum nesting depth of three is demonstrated by this particular test.
The high frequency timer interrupt adds another nesting level. See the RTOS Configuration and Usage section for a more complete explanation of the executing interrupts, and their respective priorities. The project should build without an errors or warnings, and the resultant binary programmed into the PIC32 flash memory. The constants defined in that file can be edited to suit your application.
The supplied value of Hz is useful for testing the RTOS kernel functionality but is faster than most applications require. Lowering this value will improve efficiency. FreeRTOS maintains a separate API for use in an ISR to ensure interrupt entry is as quick and as standard as possible, and to ensure that the respective API versions used from tasks and from interrupts can both be optimised for their specific usage scenarios.
The two timers used by the interrupt nesting test are allocated priorities 2 and 3 respectively. Even though they both access the same two queues, the priority 3 interrupt can safely interrupt the priority 2 interrupt. Both can interrupt the RTOS tick. Note that vPortEndScheduler has not been implemented. Interrupt service routines Interrupt service routines that cannot nest have no special requirements and can be written as per the compiler documentation.
However interrupts written in this manner will utilise the stack of whichever task was interrupted, rather than the system stack, necessitating that adequate stack space be allocated to each created task. It is therefore not recommended to write interrupt service routines in this manner. Interrupts service routines that can nest require a simple assembly wrapper, as demonstrated below. It is recommended that all interrupts be written in this manner. The T5 interrupt the interrupt for the timer that is used to demonstrate a task being unblocked from an interrupt within the PIC32MZ demo can be used as an example — the assembly code wrapper for which is replicated in Listing 1, and the C handler for which is replicated in Listing 2.
The interrupt priority is set using the Microchip provided library functions. This line MUST be included! S extension with a capitol S. Using a lower case. The context switch ensures the interrupt returns directly to the unblocked task. Performing a context switch from inside an interrupt can result in the interrupt returning to a task other than the task originally interrupted.
The C function does not use any special qualifiers or attributes — it is just a standard C function. Critical sections Exiting a critical section will always set the interrupt priority such that all interrupts are enabled, no matter what its level when the critical section was entered. Code generated by the XC32 compiler conforms to this convention so if you are writing application purely in C then this is of no concern. Care must be taken however if any hand written assembly code is used to ensure that that too conforms to the same convention.
Shadow registers The interrupt shadow registers are not used and are therefore available for use by the host application. Shadow registers should not be used within an interrupt service routine that causes a context switch. This interrupt is therefore not available for use by the application.
Book Companion Source Code
Using The FreeRTOS Real Time Kernel - Microchip PIC32 Edition (FreeRTOS…