C143 TRANSISTOR PDF

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This is a continuation of application Ser. The invention relates to a method of transferring charge from a first capacitance to a first point via a transistor circuit which exhibits a first threshold level, at least during said transfer to the first point. This known method suffers from the limitation that only charge packets of one specific polarity can be transferred.

Another method of charge transfer is employed in the so-called switched capacitance integrators which are used in integrated filters for these see for example IEEE, J. SC, No. In such integrators, charge packets are formed on a capacitance, which packets are switched to a capacitance which is connected across an operational amplifier for the purpose of negative feedback.

Such an integrator inter alia has the drawback that one operational amplifier per integrator is required, which operational amplifier continuously dissipates energy and generates noise and takes up comparatively much space in an integrated circuit. A third example of the use of the method mentioned above is a charge read-out amplifier which is inter alia employed for the nondestructive readout of charge coupled devices CCD for these, see inter alia IEEE Transactions on electronic devices, Vol.

ED, No. In this read-out amplifier the mirror charge of an input capacitance flows to a capacitance which is connected across an operational amplifier for the purpose of negative feedback, after which the charge on the negative feedback capacitance can be restored by short-circuiting said capacitance. This known application inter alia has the same drawbacks as the said integrators.

It is the object of the invention to provide a novel method of the type mentioned above, which enables the transfer of charge packets of both polarities, and which may be used advantageously in various charge transfer devices. To this end the invention is characterized by a first phase in which the transistor circuit is biased so that charge transfer from the first point to the capacitance is possible in such a way that the first capacitance can be charged to said threshold level from said first point, and a second phase in which the transistor circuit is biased so that the first capacitance can be discharged to said threshold level towards the first point.

The invention is based on the recognition that transfer of charge packets of both polarities is possible by charging the first-mentioned first capacitance from the first point and subsequently discharging it to a level which is determined by the threshold level. Ats each time after the method has been performed the first capacitance is charged again to said threshold level, the net charge transfer during operation of the method is equal to the charge which has been applied to or removed from the first capacitance between two cycles of operation of the method.

This means that both positive and negative charge packets can be transferred and that the charge condition of the first capacitance is automatically restored. Additional advantages are--because upon termination of the charge transfer the transistor circuit is not conductive and also because no bias currents are required as is the case when an operational amplifier is used--that the dissipation is minimized and complexity is reduced.

As discharging during the second phase is effected over said threshold level until a thermal equilibrium is reached, the noise level attending the charge transfer is very low relative to known methods, employing operational amplifiers.

The invention also relates to a device for carrying out the method, which device is characterized by a first point, a first capacitance, a transistor circuit included between the first capacitance and the first point, and clock signal means for biasing the transistor circuit during a first phase in such a way that charge transfer is effected from the first point to the first capacitance and for biasing the transistor circuit during a second phase in such a way that during said second phase the first capacitance is discharged towards said first point to a threshold level which is determined by the transistor circuit during said second phase.

See, for example, FIG. With respect to the biasing of the transistor circuit the device in accordance with the invention may further be characterized in that the transistor circuit comprises a first transistor with a first and a second main electrode and a control electrode, the first main electrode being connected to the first capacitance, the second main electrode being connected to the first point, and the control electrode being connected to a first source of voltage during at least said second phase for defining said threshold level, the clock signal means comprising a source of switching voltage, which source is coupled to the first point for biasing said first point during the first phase to such a voltage that charge transfer from the first point to the first capacitance is effected and for biasing said first point during the second phase to such a voltage that charge transfer from the first capacitance to said first point is effected over said threshold level.

An alternative possibility may be characterized in that the transistor comprises a first transistor having a first and a second main electrode and a control electrode, the first main electrode being connected to a second point via the first capacitance, the second main electrode being connected to the first point, and the control electrode being connected to a third point, and the clock signal means comprising a first source of switching voltage, which source is coupled to the second and third point for switching the voltage on the second and the third point to such levels during the first phase that charge transfer from the first point to the first capacitance is effected during said first phase and switching the voltage on the second and third point to such levels during the second phase that charge transfer is possible from the first capacitance to the first point, said threshold level being determined by the voltage on the third point during the second phase.

The device in accordance with the invention may suitably be used for restoring charges on capacitances, regardless of the magnitude and polarity of the signal charge. Said first point may then be connected directly to a voltage source which is switched or not. However, if the signal charge transferred is to be maintained, this is possible by adding a capacitor to the first point, on which the charge transferred appears after the method has been applied. Such a device may be employed as an integrator and is then characterized in that a transistor switch is included between a signal charge input and the first capacitance, which switch is coupled to the clock signal means in such a way that during the first and the second phase it is nonconductive and during a phase prior to the first phase, it is conductive.

With the device in accordance with the invention it is alternatively possible to apply a signal to the control electrode of the first transistor, so that said first capacitance is charged to a level determined by said signal after the use of the method in accordance with the invention.

Such a device may for example serve as a sampling circuit for sampling charge transferred to a capacitance in accordance with the inventive method and is therefore characterized in that the sampling circuit comprises a second transistor having a control electrode and a first and a second main electrode, the control electrode being connected to the input of the sampling circuit, the first electrode to an output and to a fifth capacitance and the second main electrode to a switching point which is coupled to the clock signal means in such a way that during the third phase the voltage on said switching point is switched so that first charge transfer from said switching point to the fifth capacitance is possible and that subsequently the fifth capacitance of said switching point can be discharged to a level which is determined by a voltage appearing on the input.

For the read out of, inter alia, said CCDs, the device in accordance with the invention may be characterized in that the first capacitance is connected to a signal input with the side facing the first transistor via a third transistor, whose control electrode is connected to a point of fixed voltage, and a third capacitance, said fixed voltage being selected so that during the first phase the third capacitance also receives charge from the first point and during the second phase is discharged to the first point to a level determined by the fixed voltage.

Such a device detects mirror charges of one specific polarity. A device for detecting mirror charges of the other polarity may be characterized in that via a third transistor the first point is connected to a point at such a voltage that when the third transistor conducts, the first and the second capacitance can be charged to said voltage, the control electrode of the third transistor being coupled to the clock signal means for turning on the transistor during a phase which precedes the first phase.

A device in accordance with the invention for the detection of mirror charges of both polarities, as in FIG. A device in accordance with the invention for detecting a difference between two charges may be characterized by first means for causing signal charge to be applied from a first input to the first capacitance during a third phase preceding the first phase, a second capacitance, second means for causing signal charge to be applied from a second input to the second capacitance during the third phase, switching means for connecting the first and the second capacitance in series during a fourth phase intermediate between the third and first phase, and switching means for coupling the second capacitance to the first point during the first and the second phase.

Differential embodiments in accordance with the invention are shown in FIGS. An alternative device in accordance with the invention is characterized by first means for causing signal charge to be applied from a first input to the first capacitance during a third phase preceding the first phase, a second capacitance, second means for causing signal charge to be applied from a second input to the second capacitance during the third phase, first switching means for connecting the first and the second capacitance in parallel during a fourth phase intermediate between the first and the third phase, and second switching means for coupling the second capacitance to the first point during the first and the second phase.

In comparison with the preceding device this device has the advantage that the capacitance values of the first and second capacitance need not be equal for determining the difference of two charges. A very simple device in accordance with the invention for determining the difference between two charges may be characterized by a first signal input, which is coupled to a fourth point between the first capacitance and the first transistor, a second signal input which is coupled to a fifth point, a third capacitance between the fifth point and the second point of fixed potential, the first capacitance being included between said second point of fixed potential and the fourth point, and the fifth point being coupled to the control electrode of the first transistor.

A very simple device in accordance with the invention for detecting both a positive and a negative charge, may be characterized in that the second transistor is included between the first transistor and the first point, by a third transistor between the connecting point of the first and the second transistor, and a third point, which third point is connected to a second point via a third capacitance, that the second capacitance is included between the first point and a fifth point, and that the first capacitance is included between an input terminal and a fourth point, the control electrode of the third transistor being connected to the clock signal means for turning on the third transistor during the third phase.

Such a device may simply take the form of a differential charge amplifier and to this end it is characterized by a first and second device of the last-mentioned type, the second point of each device being connected to the fourth point, which fourth point is connected to said first source of switching voltage, of which first device the first capacitance also constitutes the third capacitance of the second device and the third capacitance also constitutes the first capacitance of the second device, the control electrode of the second transistor of the first device being connected to the control electrode of the third transistor of the second device, and the control electrode of the third transistor of the first device being connected to the control electrode of the second transistor of the second device.

The method in accordance with the invention may also be employed in a delay line, bucket brigade memory or charge coupled device. Such a device is characterized in that this device in conjunction with a plurality of similar devices constitutes a series connection, the first point of each device being coupled to the first capacitance of a subsequent device, the devices alternately belonging to a first and a second group and each group being jointly coupled to the clock signal means, the first phase in the first group following the second phase in the second group and the first phase in the second group following the second phase in the first group.

In this respect it is to be noted that the use of terms like charging and discharging etc. Said operational amplifier A receives negative feedback via a capacitor C12 between the output and inverting input -.

Capacitor C11 is then charged to the voltage on input Subsequently, at instant t2, transistor T11 is turned off and capacitor C11 contains an amount of charge which is proportional to the input voltage and proportional to the capacitance value of capacitor C This charge then flows to capacitor C Each time that this cycle is repeated an amount of charge proportional to the input voltage is added to the charge present on capacitance C12, so that the voltage on output 12 is the integral of the signal on input Via a capacitor C21 the input 21 is connected to the inverting input - of an operational amplifier A.

The output of this operational amplifier A is connected to output 22 and is negatively fed back to the inverting input - via a capacitor C By means of transistor T25 the circuit can be reset by short-circuiting capacitor C It comprises a group of series-connected transistors, three of which, with the reference numerals T31, T32 and T33, being shown. Between the control electrode of each transistor and the connecting point between said transistor and the next transistor there is included a capacitor C31, C32 and C33 respectively.

The control electrodes of the transistors consecutively receive pulses of such a polarity that the relevant transistors are turned on, so that a charge present on a capacitor is transferred to the next capacitor, which is illustrated in FIG.

Diagrams a, b and c represent consecutive phases in the charge transfer, the left-hand bar in each diagram representing the charge content of a specific capacitor, for example C31, the center bar the threshold constituted by the transistor, for example T32, which follows said capacitor, and the right-hand bar the charge content of the next capacitor, for example C In the absence of a signal all capacitors are charged to a reference level VL.

In FIG. If, as is shown in FIG. Increasing the voltage on the control electrode of transistor T32 resets the circuit to the initial position, after which by means of a pulse on the control electrode of transistor T33 the signal charge packet q can be transferred to capacitor C This arrangement comprises a capacitance C41 between a point 41 and a transistor T40 which is included between the capacitance C41 and a terminal The control electrode of transistor T40 is connected to a point As the case may be, a capacitance C42, included between point 42 and a point 44, may be added to point The method in accordance with the invention is explained with reference to FIG.

Transistor T40 represents a threshold VL between a capacitor C41 and capacitor C42 in that the voltage on the control electrode connection 43, when ignoring the threshold voltage Vth of the transistor T40 itself, is equal to VL or in that just before the situation shown in FIG. Capacitor 42 contains a reference charge Q1. In the situation shown in FIG. A negative signal charge -q will remain in capacitor C In order to enable the transfer of negative signal charges a positive voltage pulse is applied to point 44, which via capacitor C42 is transferred to point The situation then obtained is outlined in FIG.

In this situation both capacitor C42 and capacitor C41 are filled with charge above the threshold VL. If subsequently the voltage on point 44 is reduced to the original level, the situation of FIG. If a clock signal is applied to the control electrode of transistor T40, said clock signal may be selected so that after the charge transfer process as shown in FIGS.

This yields the situation of FIG. If desired, voltage amplification may be obtained by selecting the capacitance value of capacitor C42 to be smaller than that of capacitor C If the circuit of FIG.

The situation upon termination of the charge transfer process is then as outlined in FIG. The voltage variations shown in FIG. Instead of pulsating the voltage on point 42 or 44, it is alternatively possible to maintain said point 42 or 44 at a fixed voltage and to briefly reduce the voltage on point 41 and point 43, so that the charge transfer outlined in FIG.

This circuit arrangement in accordance with FIG. Via a transistor T52 with a control electride connection 56 and a transisor T50, whose control electrode is connected to a point of fixed potential, in the present example earth, capacitor C51 is connected to an output Between output 52 and a switching point 54 a capacitor C52 is included.

In the circuit of FIG. At instant t1 transistor T51 is turned on, so that capacitor C51 is charged or discharged to the voltage on input At instant t2 transistor T51 is cut off and transistor T52 is turned on, after which the charge transfer process described with reference to FIGS. As a result of this, charge is transferred from capacitor C52 to capacitor C51 over the threshold VL so as to replenish a negative signal charge -q, if any--the situation corresponding to the situation shown in FIG.

At instant t3 the voltage on point 54 is reduced again, so that capacitor C51 discharges to the threshold level VL--the situation after this corresponds to the situation shown in FIG.

At this instant the positive or negative signal charge present in capacitor C51 at the instant t2 is added to the charge already present in capacitor C52 and the charge in capacitor C51 is restored to the reference level Q0.

The function of the circuit arrangement in accordance with FIG. In order to prevent transistors T50 and T52 from being turned on a voltage pulse may then be applied to the control electrode of transistor T An other possibility is to bring the clock signal at a reference level during said periods, which level corresponds to an output voltage around the level VL shown in FIG.

In the case of integrators it may be desirable to integrate a plurality of signals together. In the arrangement of FIG. The signal charges on capacitors C51 and C61 may be transferred to capacitor C52 by turning on transistors T52 and T62 and applying a pulse to point This circuit operates in a similar way as that of FIG.

The electrode corresponding to capacitor C51 should then be connected to a negative voltage - so that it can also contain negative signal charges; this is because the channel in the present example is of the p-type. With the circuit of FIG. The circuit is identical to that of FIG.

In order to illustrate the operation of the circuit of FIG. At instant t3 the voltages on points 86 and 83 are reduced, so that the thresholds of transistors T82 and T80 drop below the charge level on capacitor C82 and charge transfer to the left is possible FIG. In a similar way as with the circuit of FIG.

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BC143 TRANSISTOR. Datasheet pdf. Equivalent

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